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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. b 11/14/03 i s61lpd25632t is61lpd25636t is61lpd51218t issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control linear burst sequence control using mode input three chip enable option for simple depth expansion and address pipelining common data inputs and data outputs jedec 100-pin tqfp power supply +3.3v v dd +3.3v or 2.5 v ddq (i/o) auto power-down during deselect double cycle deselect snooze mode for reduced-power standby t version (three chips selects) description the issi is61lpd25632t, is61lpd25636t, and is61lpd51218t are high-speed, low-power synchronous static rams designed to provide burstable, high-performance memory for communication and networking applications. the is61lpd25632t is organized as 262,144 words by 32 bits and the is61lpd25636t is organized as 262,144 words by 36 bits. the is61lpd51218t is organized as 524,288 words by 18 bits. fabricated with issi 's advanced cmos technology, the device integrates a 2-bit burst counter, high- speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ). input combined with one or more individual byte write signals ( bwx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the adv (burst address ad- vance) input pin. the mode pin is used to select the burst sequence order. linear burst is achieved when this pin is tied low. inter- leave burst is achieved when this pin is tied high or left floating. 256k x 32, 256k x 36, 512k x 18 synchronous pipelined, double-cycle deselect static ram november 2003 fast access time symbol parameter -166 units t kq clock access time 3.5 ns t kc cycle time 6 ns frequency 166 mhz
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 block diagram 18/19 binary counter bwa gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register ce d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bwd ce (t) ce2 (t) ce2 (t) bwb bwc 256kx32; 256kx36; 512kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 4 oe dqa - dqd 32, 36, or 18 32, 36, or 18 a (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18)
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 11/14/03 pin configuration 100-pin tqfp (t version) 256k x 32 nc dqb dqb v ddq gnd dqb dqb dqb dqb gnd v ddq dqb dqb gnd nc v dd zz dqa dqa v ddq gnd dqa dqa dqa dqa gnd v ddq dqa dqa nc a a ce ce2 bwd bwc bwb bwa ce2 v dd gnd clk gw bwe oe ads c adsp adv a a nc dqc dqc v ddq gnd dqc dqc dqc dqc gnd v ddq dqc dqc nc v dd nc gnd dqd dqd v ddq gnd dqd dqd dqd dqd gnd v ddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 100-pin tqfp (t version) 256k x 36 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o pin configuration dqpb dqb dqb v dd q gnd dqb dqb dqb dqb gnd v dd q dqb dqb gnd nc v dd zz dqa dqa v dd q gnd dqa dqa dqa dqa gnd v dd q dqa dqa dqpa a a ce ce2 bwd bwc bwb bwa ce2 v dd gnd clk gw bwe oe adsc adsp adv a a dqpc dqc dqc v dd q gnd dqc dqc dqc dqc gnd v dd q dqc dqc nc v dd nc gnd dqd dqd v dd q gnd dqd dqd dqd dqd gnd v dd q dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 11/14/03 pin configuration 512k x 18 100-pin tqfp (t version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o a nc nc v ddq gnd nc dqpa dqa dqa gnd v ddq dqa dqa gnd nc v dd zz dqa dqa v ddq gnd dqa dqa nc nc gnd v ddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 v dd gnd clk gw bwe oe adsc adsp adv a a nc nc nc v ddq gnd nc nc dqb dqb gnd v ddq dqb dqb v dd v dd nc gnd dqb dqb v ddq gnd dqb dqb dqpb nc gnd v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd v dd nc a a a a a a a a 46 47 48 49 50
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 truth table (1-8) operation address ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 zz adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l xxxxl-h high-z deselect cycle, power-down none l h x l l xxxxl-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h xxxxxx high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l hhhhll-h q read cycle, suspend burst current x x x l hhhhhl-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x hhhhl-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: 1. x means ?don?t care.? h means logic high. l means logic low. 2. for write , l means one or more byte write enable signals ( bwa , bwb , bwc or bwd ) and bwe are low or gw is low. write = h for all bwx , bwe , gw high. 3. bwa enables writes to dqa?s and dqpa. bwb enables writes to dqb?s and dqpb. bwc enables writes to dqc?s and dqpc. bwd enables writes to dqd?s and dqpd. dqpa and dqpb are only available on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clk. see write timing diagram for clarification.
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 11/14/03 interleaved burst address table (mode = v dd or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) 0,0 1,0 0,1 a1', a0' = 1,1 function gw gw gw gw gw bwe bwe bwe bwe bwe bwa bwa bwa bwa bwa bwb bwb bwb bwb bwb bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v 5% 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v 5% 2.5v 5% partial truth table
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.5 v v in voltage relative to gnd for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relatiive to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. dc electrical characteristics (over operating range) 2.5v (i/o) 3.3v (i/o) symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.0 ? 2.4 ? v i oh = 1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 1.7 v dd + 0.3 2.0 v dd + 0.3 v v il input low voltage ?0.3 0.7 ?0.3 0.8 v i li input leakage current gnd v in v dd (1) ?5 5 ?5 5 a i lo output leakage current gnd v out v ddq , oe = v i ?5 5 ?5 5 a
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 11/14/03 power supply characteristics (1) (over operating range) -166 max max symbol parameter test conditions x18 x36 unit i cc ac operating device selected, com. 120 125 ma supply current oe = v ih , zz v il , ind. 130 135 all inputs v il or v ih , cycle time t kc min. i sb standby current device deselected, com. 50 50 ma ttl input v dd = max., ind. 55 55 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 30 30 ma cmos input v dd = max., ind. 40 40 v in gnd + 0.2v or v dd ? 0.2v f = 0 note: 1. mode pin has an internal pullup and should be tied to v dd or gnd. it exhibits 30 a maximum leakage current when tied to gnd + 0.2v or v dd ? 0.2v.
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1ns input and output timing 1.5v and reference level output load see figures 1 and 2 figure 1 figure 2 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o output load equivalent z o = 50 ? 1.5v 50 ? output 317 ? 5 pf including jig and scope 351 ? output +3.3v
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 11/14/03 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1 ns input and output timing 1.25v and reference level output load see figures 3 and 4 figure 3 figure 4 z o = 50 ? 1.25v 50 ? output 1,667 ? 5 pf including jig and scope 1,538 ? output +2.5v 2.5v i/o output load equivalent
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 read/write cycle switching characteristics (over operating range) -166 symbol parameter min. max. unit f max clock frequency ? 166 ns t kc cycle time 6 ? ns t kh clock high pulse width 2.3 ? ns t kl clock low pulse width 2.3 ? ns t kq clock access time ? 3.5 ns t kqx (1) clock high to output invalid 1.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? ns t kqhz (1,2) clock high to output high-z ? 3.5 ns t oeq output enable to output valid ? 3.5 ns t oelz (1,2) output enable to output low-z 0 ? ns t oehz (1,2) output enable to output high-z ? 3.5 ns t as address setup time 1.5 ? ns t ss address status setup time 1.5 ? ns t ws write setup time 1.5 ? ns t ces chip enable setup time 1.5 ? ns t avs address advance setup time 1.5 ? ns t ah address hold time 0.5 ? ns t sh address status hold time 0.5 ? ns t wh write hold time 0.5 ? ns t ceh chip enable hold time 0.5 ? ns t avh address advance hold time 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 1,2,3,4.
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 11/14/03 read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 write cycle switching characteristics (over operating range) -166 symbol parameter min. max. unit t kc cycle time 6 ? ns t kh clock high pulse width 2.3 ? ns t kl clock low pulse width 2.3 ? ns t as address setup time 1.5 ? ns t ss address status setup time 1.5 ? ns t ws write setup time 1.5 ? ns t ds data in setup time 1.5 ? ns t ces chip enable setup time 1.5 ? ns t avs address advance setup time 1.5 ? ns t ah address hold time 0.5 ? ns t sh address status hold time 0.5 ? ns t dh data in hold time 0.5 ? ns t wh write hold time 0.5 ? ns t ceh chip enable hold time 0.5 ? ns t avh address advance hold time 0.5 ? ns
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. b 11/14/03 write cycle timing single write data out data in oe ce2 ce2 ce bwx bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2a 2b
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t 16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 11/14/03 snooze mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z snooze mode electrical characteristics symbol parameter cond itions min. max. unit i sb 2 current during snooze mode zz vih, com. ? 30 ma zz vih, ind. ? 40 t pus zz inactive to input sampled 2 ? cycle t zzi zz active to snooze current ? 2 cycle t rzzi zz inactive to exit snooze current 0 ? ns
issi ? is61lpd25632t, is61lpd25636t, is61lpd51218t integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. b 11/14/03 (t version) industrial range: -40c to +85c speed order part number package 166mhz is61lpd 25632t-166tqi tqfp is61lpd 51218t-166tqi tqfp ordering information (t version) commercial range: 0c to +70c speed order part number package 166mhz is61lpd25632t-166tq tqfp IS61LPD25636T-166TQ tqfp is61lpd51218t-166tq tqfp
integrated silicon solution, inc. ? 1-800-379-4774 packaging information issi ? pk13197lq rev. d 05/08/03 tqfp (thin quad flat pack package) package code: tq thin quad flat pack (tq) millimeters inches millimeters inches symbol min max min max min max min max ref. std. no. leads (n) 100 128 a ? 1.60 ? 0.063 ? 1.60 ? 0.063 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011 d 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874 d1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791 e 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638 e1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555 e 0.65 bsc 0.026 bsc 0.50 bsc 0.020 bsc l 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030 l1 1.00 ref. 0.039 ref. 1.00 ref. 0.039 ref. c0 o 7 o 0 o 7 o 0 o 7 o 0 o 7 o notes: 1. all dimensioning and tolerancing conforms to ansi y14.5m-1982. 2. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 do include mold mismatch and are determined at datum plane -h-. 3. controlling dimension: millimeters. d d1 e e1 1 n a2 a a1 e b seating plane c l1 l

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